DS21554L

Product Summary

The DS21554L is a single-chip transceiver (SCT). The DS21554L contains all the necessary functions to connect to E1 lines. The on-board clock/data recovery circuitry coverts the AMI/HDB3 E1 waveforms to an NRZ serial stream. The DS21554L automatically adjusts to E1 22AWG (0.6mm) twistedpair cables from 0 to over 2km in length. The on-board jitter attenuator (selectable to either 32 bits or 128 bits) can be placed in either the transmit or receive data paths. The framer locates the frame and multiframe boundaries and monitors the data stream for alarms. It is also used for extracting and inserting signaling data, Si, and Sa-bit information. The on-board HDLC controller can be used for Sa-bit links or DS0s. The DS21554L contains a set of internal registers that the user can access to control the operation of the units. Quick access through the parallel control port allows a single controller to handle many E1 lines.

Parametrics

DS21554L absolute maximum ratings: (1)Voltage Range on Any Pin Relative to Ground: -1.0V to +6.0V; (2)Operating Temperature Range for DS21354L/DS21554L: 0℃ to +70℃; (3)Operating Temperature Range for DS21354LN/DS21554LN: -40℃ to +85℃; (4)Storage Temperature Range: -55℃ to +125℃; (5)Input Capacitance CIN: 5 pF; (6)Output Capacitance COUT: 7 pF; (7)Supply Current at 5V IDD: 75 mA; (8)Supply Current at 3.3V IDD: 75 mA.

Features

DS21554L features: (1)Complete E1 (CEPT)PCM-30/ISDN-PRI Transceiver Functionality; (2)On-Board Long- and Short-Haul Line Interface for Clock/Data Recovery and Waveshaping; (3)32-Bit or 128-Bit Crystal-Less Jitter Attenuator; (4)Frames to FAS, CAS, CCS, and CRC4 Formats; (5)Integral HDLC Controller with 64-Byte Buffers Configurable for Sa Bits, DS0, or Sub-DS0 Operation; (6)Dual Two-Frame Elastic Store Slip Buffers that can Connect to Asynchronous Backplanes up to 8.192MHz; (7)Interleaving PCM Bus Operation; (8)8-Bit Parallel Control Port that can be used Directly on Either Multiplexed or Nonmultiplexed Buses (Intel or Motorola); (9)Extracts and Inserts CAS Signaling; (10)Detects and Generates Remote and AIS Alarms; (11)Programmable Output Clocks for Fractional E1, H0, and H12 Applications; (12)Fully Independent Transmit and Receive Functionality; (13)Full Access to Si and Sa Bits Aligned with CRC-4 Multiframe; (14)Four Separate Loopback Functions for Testing Functions; (15)Large Counters for Bipolar and Code Violations, CRC4 Codeword Errors, FAS Word Errors, and E Bits; (16)IEEE 1149.1 JTAG-Boundary Scan Architecture; (17)Pin Compatible with DS2154/52/352/552 SCTs; (18)3.3V (DS21354)or 5V (DS21554)Supply; Low- Power CMOS; (19)100-pin LQFP package (14mm x 14mm).

Diagrams