AD9516-3BCPZ

Product Summary

The AD9516-3BCPZ is a 14-Output Clock Generator with Integrated 2.0 GHz VCO. The AD9516-3BCPZ provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz may be used. The applications of the AD9516-3BCPZ include Low jitter, low phase noise clock distribution, Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs, High performance wireless transceivers, High performance instrumentation, Broadband infrastructure and ATE.

Parametrics

AD9516-3BCPZ absolute maximum ratings: (1)VS, VS_LVPECL GND: -0.3 V to +3.6 V; (2)VCP GND: -0.3 V to + 5.8 V; (3)REFIN, REFIN GND: -0.3 V to VS + 0.3 V; (4)REFIN REFIN: -3.3 V to +3.3 V; (5)RSET GND: -0.3 V to VS + 0.3 V; (6)CPRSET GND: -0.3 V to VS + 0.3 V; (7)CLK, CLK GND: -0.3 V to VS + 0.3 V; (8)CLK CLK: -1.2 V to +1.2 V; (9)SCLK, SDIO, SDO, CS GND: -0.3 V to VS + 0.3 V; (10)OUT0, OUT0, OUT1, OUT1,OUT2, OUT2, OUT3, OUT3, OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7, OUT8, OUT8, OUT9, OUT9, GND: -0.3 V to VS + 0.3 V; (11)SYNC GND: -0.3 V to VS + 0.3 V; (12)REFMON, STATUS, LD GND: -0.3 V to VS + 0.3 V; (13)Junction Temperature: 150℃; (14)Storage Temperature Range: -65 to +150℃; (15)Lead Temperature (10 sec): 300℃.

Features

AD9516-3BCPZ features: (1)Low phase noise, phase-locked loop; (2)On-chip VCO tunes from 1.75 GHz to 2.25 GHz; (3)External VCO/VCXO to 2.4 GHz optional; (4)1 differential or 2 single-ended reference inputs; (5)Reference monitoring capability; (6)Auto and manual reference switchover/holdover modes; (7)Autorecover from holdover; (8)Accepts references to 250 MHz; (9)Programmable delays in path to PFD; (10)Digital or analog lock detect, selectable; (11)3 pairs of 1.6 GHz LVPECL outputs ; (12)Each pair shares 1 to 32 dividers with coarse phase delay; (13)Additive output jitter 225 fS rms; (14)Channel-to-channel skew paired outputs <10 ps; (15)2 pairs of 800 MHz LVDS clock outputs; (16)Each pair shares two cascaded 1 to 32 dividers with coarse phase delay; (17)Additive output jitter 275 fS rms.

Diagrams