Product Summary
The SN74LV138DBR is a 3-line to 8-line decoder/demultiplexer. It is designed for 2-V to 5.5-V VCC operation. The SN74LV138DBR is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.
Parametrics
SN74LV138DBR absolute maximum ratings: (1)Supply voltage range: -0.5V to 7V; (2)Input voltage range: -0.5V to 7V; (3)Voltage range applied to any output in the high-impedance or power-off state:–0.5V to 7V; (4)Output voltage range: -0.5V to VCC+0.5V; (5)Input clamp current VI<0: -20mA; (6)Output clamp current VO<0: -50mA; (7)Continuous output current VO=0 to VCC: ±25mA; (8)Continuous current through VCC or GND: ±50mA; (9)θJA Package thermal impedance: 82℃/W; (10)Storage temperature range: -65℃ to 150℃.
Features
SN74LV138DBR features: (1)2-V to 5.5-V VCC Operation; (2)Max tpd of 9.5 ns at 5 V; (3)Typical VOLP (Output Ground Bounce)<0.8V at VCC =3.3V, TA=25℃; (4)Typical VOHV (Output VOH Undershoot)>2.3V at VCC=3.3V, TA=25℃; (5)Support Mixed-Mode Voltage Operation on All Ports; (6)Ioff Supports Partial-Power-Down Mode Operation; (7)Latch-Up Performance Exceeds 250mA Per JESD 17; (8)ESD Protection Exceeds JESD 22: 2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101).
Diagrams
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![]() SN7400DE4 |
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![]() SN7400DG4 |
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![]() Gates (AND / NAND / OR / NOR) Quad 2-input Pos- NAND |
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![]() SN7400DR |
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![]() IC QUAD 2IN POS-NAND GATE 14SOIC |
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![]() SN7400DRE4 |
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![]() IC QUAD 2IN POS-NAND GATE 14SOIC |
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![]() Negotiable |
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