DS90LV110TMTC

data/clock distributor, TSSOP, -0.3V to +4V

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Price:: US $0.00~0.20 / piece [Get Latest Price]

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PartNumber:: DS90LV110TMTC

Brand:: National Semiconductor - NS | Pack: TSSOP | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2011-07-22

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Part Number:DS90LV110TMTC
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Product Summary

The DS90LV110TMTC is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The DS90LV110TMTC allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. The DS90LV110TMTC can also be used for clock distribution up to 400MHz.

Parametrics

DS90LV110TMTC absolute maximum ratings: (1)Supply Voltage (VDD-VSS): -0.3V to +4V; (2)LVCMOS/LVTTL Input Voltage (EN): -0.3V to (VCC + 0.3V); (3)LVDS Receiver Input Voltage (IN+, IN.): -0.3V to +4V; (4)LVDS Driver Output Voltage (OUT+, OUT.): -0.3V to +4V; (5)Junction Temperature: +150°C; (6)Storage Temperature Range: -65℃ to +150℃; (7)Lead Temperature (Soldering, 4 sec.): +260℃; (8)Maximum Package Power Dissipation at 25℃: 1.209 W; (9)Package Derating: 9.67 mW/℃ above +25℃; (10)ESD Rating: (HBM, 1.5kW, 100pF) > 4 kV, (EIAJ, 0W, 200pF) > 250 V.

Features

DS90LV110TMTC features: (1)Low jitter 800 Mbps fully differential data path; (2)145 ps (typ) of pk-pk jitter with PRBS = 223-1 data pattern at 800 Mbps; (3)Single +3.3 V Supply; (4)Less than 413 mW (typ) total power dissipation; (5)Balanced output impedance; (6)Output channel-to-channel skew is 35ps (typ); (7)Differential output voltage (VOD) is 320mV (typ) with 100W termination load; (8)LVDS receiver inputs accept LVPECL signals; (9)Fast propagation delay of 2.8 ns (typ); (10)Receiver input threshold < ±100 mV; (11)28 lead TSSOP package; (12)Conforms to ANSI/TIA/EIA-644 LVDS standard.