(China (Mainland))
Product Summary
The TPS51100DGQR is a 3-A sink/source tracking termination regulator. It is specifically designed for low-cost/low-external component count systems, where space is a premium. The TPS51100DGQR maintains fast transient response only requiring 20-μF (2 × 10μF) of ceramic output capacitance. The TPS51100DGQR supports remote sensing functions and all features required to power the DDR and DDR2 VTT bus termination according to the JEDEC specification. In addition, the TPS51100DGQR includes integrated sleep-state controls placing VTT in High-Z in S3 (suspend to RAM) and soft-off for VTT and VTTREF in S5 (suspend to disk). The device is used in DDR, DDR2 Memory Termination, SSTL-2, SSTL-18 and HSTL Termination.
Parametrics
TPS51100DGQR absolute maximum ratings: (1)Input voltage range: VIN, VLDOIN, VTTSNS, VDDQSNS, S3, S5: -0.3 to 6 V, PGND: -0.3 to 0.3 V; (2)Output voltage range: VTT, VTTREF: -0.3 to 6 V; (3)Operating ambient temperature range, TA: -40 to 85 ℃; (4)Storage temperature, Tstg: -55 to 150 ℃.
Features
TPS51100DGQR features: (1)Input Voltage Range: 4.75 V to 5.25 V; (2)VLDOIN Voltage Range: 1.2 V to 3.6 V; (3)3-A Sink/Source Termination Regulator Includes Droop Compensation; (4)Requires Only 20-μF Ceramic Output Capacitance; (5)Supports High-Z in S3 and Soft-Off in S5; (6)1.2-V Input (VLDOIN) Helps Reduce Total Power Dissipation; (7)Integrated Divider Tracks 1/2 VDDQSNS for VTT and VTTREF; (8)Remote Sensing (VTTSNS); (9)± 20-mV Accuracy for VTT and VTTREF; (10)10-mA Buffered Reference (VTTREF); (11)Built-In Soft-Start, UVLO and OCL; (12)Thermal Shutdown; (13)Supports JEDEC Specifications.
Diagrams
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 TPS51100DGQR |
Texas Instruments |
Low Dropout (LDO) Regulators 3A Source/Sink DDR Terminator Regulator |
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TPS51100DGQRG4 |
Texas Instruments |
Low Dropout (LDO) Regulators 3A Source/Sink DDR Terminator Regulator |
Data Sheet |
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