(China (Mainland))
Product Summary
The SN74ABT573ADBR is an octal transparent D-type latch. The SN74ABT573ADBR features 3-state designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The SN74ABT573ADBR is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Parametrics
SN74ABT573ADBR absolute maximum ratings: (1)Supply voltage range, VCC: 0.5V to 7V; (2)Input voltage range, VI: Except I/O ports: 0.5V to 7V; (3)I/O ports: 0.5V to 7V; (4)Voltage range applied to any output in the high-impedance or power-off state, VO: 0.5V to 7V; (5)Output voltage range applied in the high or low state, VO: 0.5V to VCC + 0.5V; (6)Input clamp current, IIK (VI＜0): 20 mA; (7)Output clamp current, IOK (VO＜0): 50 mA; (8)Continuous output current, IO (VO = 0 to VCC): ±35 mA; (9)Continuous current through VCC or GND: ±70 mA; (10)Package thermal impedance, θJA: DB package: 70℃/W; (11)DGV package: 92℃/W; (12)DW package: 58℃/W; (13)GQN package: 78℃/W; (14)NS package: 60℃/W; (15)PW package: 83℃/W; (16)RGY package: 37℃/W; (17)Storage temperature range, Tstg: 65℃ to 150℃.
Features
SN74ABT573ADBR features: (1)Typical VOLP (Output Ground Bounce)＜1 V at VCC = 5 V, TA = 25℃; (2)High-Drive Outputs (.32-mA IOH, 64-mA IOL); (3)Ioff Supports Partial-Power-Down Mode Operation; (4)Latch-Up Performance Exceeds 500 mA Per; (5)JEDEC Standard JESD 17; (6)ESD Protection Exceeds JESD 22; (7)2000-V Human-Body Model (A114-A); (8)200-V Machine Model (A115-A).
Diagrams
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 SN74ABT573ADBR |
Texas Instruments |
Latches Tri-St Octal D-Type |
Data Sheet |
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SN74ABT573ADBRE4 |
Texas Instruments |
Latches Tri-St Octal D-Type |
Data Sheet |
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SN74ABT573ADBRG4 |
Texas Instruments |
Latches Octal Transp D-Type |
Data Sheet |
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