MPC8247VRTIEA

Product Summary

The MPC8247VRTIEA is an integrated communications processor. The MPC8247VRTIEA contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specification. The MPC8247VRTIEA.13μm (HiP7) member of the PowerQUICC II family of integrated communications processors. The MPC8247VRTIEA includes on a single chip a 32-bit PowerPC core that incorporates memory management units (MMUs) and instruction and data caches and that implements the PowerPC instruction set; a modified communications processor module (CPM); and an integrated security engine (SEC) for encryption.

Parametrics

MPC8247VRTIEA absolute maximum ratings: (1)Core supply voltage VDD: -0.3 to 2.25 V; (2)PLL supply voltage VCCSYN: -0.3 to 2.25 V; (3)I/O supply voltage VDDH: -0.3 to 4.0 V; (4)Input voltage VIN GND: (-0.3)to 3.6 V; (5)Junction temperature Tj: 120 °C; (6)Storage temperature range T STG: (-55)to (+150)°C; (7)Input leakage current, V IN = VDDH I IN: 10 μA.

Features

MPC8247VRTIEA features: (1)G2_LE core and CPM can run at different frequencies for power/performance optimization; (2)Bus supports multiple master designs—up to two external masters; (3)Supports single transfers and burst transfers; (4)64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller; (5)Programmable host bridge and agent; (6)32-bit data bus, 66 MHz, 3.3 V; (7)Synchronous and asynchronous 60x and PCI clock modes; (8)All internal address space available to external PCI host; (9)DMA for memory block transfers; (10)PCI-to-60x address remapping; (11)Clock synthesizer; (12)Reset controller; (13)Real-time clock (RTC)register; (14)Periodic interrupt timer; (15)Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other user-definable peripherals; (16)Byte write enables; (17)32-bit address decodes with programmable bank size; (18)Three user programmable machines, general-purpose chip-select machine, and page mode pipeline SDRAM machine; (19)Byte selects for 64-bit bus width (60x); (20)Dedicated interface logic for SDRAM.

Diagrams