Product Summary
The SN74LVC2G32YEAR is a dual 2-input positive-OR gate. The SN74LVC2G32YEAR is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G32YEAR performs the Boolean function Y= A+B or Y= A × B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Parametrics
SN74LVC2G32YEAR absolute maximum ratings: (1)Supply voltage range, VCC: 0.5 V to 6.5 V; (2)Input voltage range, VI (see Note 1): 0.5 V to 6.5 V; (3)Voltage range applied to any output in the high-impedance or power-off state, VO(see Note 1): 0.5 V to 6.5 V; (4)Voltage range applied to any output in the high or low state, VO (see Notes 1 and 2):0.5 V to VCC + 0.5 V; (5)Input clamp current, IIK (VI<0): 50 mA; (6)Output clamp current, IOK (VO<0): 50 mA; (7)Continuous output current, IO:±50 mA; (8)Continuous current through VCC or GND: ±100 mA; (9)Package thermal impedance, θJA (see Note 3): 140℃/W; (10)Storage temperature range, Tstg: 65℃ to 150℃.
Features
SN74LVC2G32YEAR features: (1) Available in the Texas Instruments NanoStar and NanoFree. Packages; (2)Supports 5-V VCC Operation; (3)Inputs Accept Voltages to 5.5 V; (4)Max tpd of 3.8 ns at 3.3 V; (5)Low Power Consumption, 10-μA Max ICC; (6)±24-mA Output Drive at 3.3 V; (7)Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25℃; (8)Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25℃; (9)Ioff Supports Partial-Power-Down Mode Operation; (10) Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II; (11) ESD Protection Exceeds JESD 22:2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101).
Diagrams
Image | Part No | Mfg | Description | Pricing (USD) |
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SN74LVC2G32YEAR |
IC DUAL 2-IN POS-OR GATE 8-DSBGA |
Data Sheet |
Negotiable |
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