(China (Mainland))
Product Summary
The SN74LVC1G32DBVR single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G32DBVR performs the Boolean function Y=A+B or Y =A·B in positive logic. NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package. The SN74LVC1G32DBVR is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
Parametrics
SN74LVC1G32DBVR absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 6.5 V; (2)Input voltage range, VI: -0.5 V to 6.5 V; (3)Voltage range applied to any output in the high-impedance or power-off state, VO: -0.5 V to 6.5 V; (4)Voltage range applied to any output in the high or low state, VO: -0.5 V to VCC + 0.5 V; (5)Input clamp current, IIK (VI < 0): -50 mA; (6)Output clamp current, IOK (VO < 0): -50 mA; (7)Continuous output current, IO: ±50 mA; (8)Continuous current through VCC or GND: ±100 mA; (9)Package thermal impedance, θJA: DBV package: 206℃/W, DCK package: 252℃/W, DRL package: 142℃/W, YEA/YZA package: 154℃/W, YEP/YZP package: 132℃/W; (10)Storage temperature range, Tstg: -65℃ to 150℃.
Features
SN74LVC1G32DBVR features: (1)Available in the Texas Instruments NanoStar and NanoFree Packages; (2)Supports 5-V VCC Operation; (3)Inputs Accept Voltages to 5.5 V; (4)Max tpd of 3.6 ns at 3.3 V; (5)Low Power Consumption, 10-μA Max ICC; (6)±24-mA Output Drive at 3.3 V; (7)Ioff Supports Partial-Power-Down Mode Operation; (8)Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II; (9)ESD Protection Exceeds JESD 22: 2000-V Human-Body Model (A114-A), 200-V Machine Model (A115-A), 1000-V Charged-Device Model (C101).
Diagrams
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 SN74LVC1G32DBVR |
Texas Instruments |
Gates (AND / NAND / OR / NOR) Single 2-Input Pos |
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SN74LVC1G32DBVRE4 |
Texas Instruments |
Gates (AND / NAND / OR / NOR) SNGL 2 Input Pos OR Gate |
Data Sheet |
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SN74LVC1G32DBVRG4 |
Texas Instruments |
Gates (AND / NAND / OR / NOR) SNGL 2 Input Pos OR Gate |
Data Sheet |
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