(China (Mainland))
Product Summary
The SN74LV165APWR is a parallel-load 8-bit shift register. It is designed for 2-V to 5.5-V VCC operation. When the SN74LV165APWR is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. The SN74LV165APWR features a clock-inhibit function and a complemented serial output, QH. It is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.
Parametrics
SN74LV165APWR absolute maximum ratings: (1)Supply voltage range, VCC: -0.5 V to 7 V; (2)Input voltage range, VI: -0.5 V to 7 V; (3)Voltage range applied to any output in the high-impedance or power-off state, VO: -0.5 V to 7 V; (4)Output voltage range, VO: -0.5 V to VCC + 0.5 V; (5)Input clamp current, IIK (VI < 0): -20 mA; (6)Output clamp current, IOK (VO < 0): -50 mA; (7)Continuous output current, IO (VO = 0 to VCC): ±25 mA; (8)Continuous current through VCC or GND: ±50 mA; (9)Storage temperature range, Tstg: -65℃ to 150℃.
Features
SN74LV165APWR features: (1)2-V to 5.5-V VCC Operation; (2)Max tpd of 10.5 ns at 5 V; (3)Support Mixed-Mode Voltage Operation on All Ports; (4)Ioff Supports Partial-Power-Down Mode Operation; (5)Latch-Up Performance Exceeds 250 mA Per JESD 17; (6)ESD Protection Exceeds JESD 22.
Diagrams
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 SN74LV165APWR |
Texas Instruments |
Counter Shift Registers 8-Bit Parallel Load |
Data Sheet |
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SN74LV165APWRE4 |
Texas Instruments |
Counter Shift Registers Parallel-Load 8-Bit Shift Register |
Data Sheet |
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SN74LV165APWRG4 |
Texas Instruments |
Counter Shift Registers Parallel-Load 8-Bit Shift Register |
Data Sheet |
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SN74LV165APWRG3 |
Texas Instruments |
Registers Parallel-Load 8B Shift Reg |
Data Sheet |
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