74LVCH162373ADL

Product Summary

The 74LVCH162373ADL is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (LE) input and one output enable (OE) are provide for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation,outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. The 74LVCH162373ADL consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes.

Parametrics

74LVCH162373ADL absolute maximum rating system: (1)VCC, DC supply voltage: -0.5 V min. +6.5 V max.; (2)IIK, DC input diode current: When VI < 0, -50 mA max.; (3)VI, DC input voltage: note 1 -0.5 +5.5 V; (4)IOK, DC output diode current: VO > VCC or VO < 0 - ±50 mA; (5)VO, DC output voltage output HIGH or LOW: note 1 -0.5 V min. VCC + 0.5 V max. output 3-state: note 1 -0.5 min. +6.5 V max.; (6)IO, DC output diode current: VO = 0 to VCC - ±50 mA max.; (7)ICC, IGND DC VCC or GND current: - ±100 mA max.; (8)Tstg, storage temperature: -65 min. +150℃ max.; (9)Ptot, power dissipation plastic shrink mini-pack (SSOP and TSSOP): above 60℃ derate linearly with 5.5 mW/K, 500 mW max.

Features

74LVCH162373ADL features: (1) ESD protection: HBM EIA/JESD22-A114-A, exceeds 2000 V, MM EIA/JESD22-A115-A, exceeds 200 V. 5 V tolerant input/output for interfacing with 5 V logic.; (2)Wide supply voltage range of 1.2 to 3.6 V; (3)Complies with JEDEC standard no. 8-1A; (4)CMOS low power consumption ; (5)MULTIBYTE ; (6)flow-through standard pin-out architecture ; (7)Low inductance multiple power and ground pins for minimum noise and ground bounce; (8)Direct interface with TTL levels ; (9)All data inputs have bus hold (74LVCH162373A only) ; (10)High impedance when VCC = 0; (11)Power off disables outputs, permitting live insertion.

Diagrams